1. Field of the Invention
The present invention relates to the field of scan testing; more particularly, the present invention relates to a method and apparatus for performing scan testing on dynamic circuits, such as domino logic.
2. Description of Related Art
A typical integrated circuit has combinational logic blocks, which may include dynamic circuits, such as domino logic. These combinational logic blocks are coupled through latches controlled by a system clock. In order to test the functionality and performance of a combinational logic block, various combinations of stimulus conditions are selected according to well-known methods. In order to apply the desired stimulus to a combinational logic block, a sequence of operations may need to be performed. In a complex integrated circuit, the time to apply this sequence of operations can be burdensome.
Scan testing is a well-known technique for implementing a scan chain which serially accepts data that is applied to critical inputs of these combinational logic blocks. The ability to directly control inputs of internal combinational logic simplifies the preparation process for a test of the combinational logic blocks. Each of the scan cells have a scan input latch and a scan output latch that are serially coupled to adjacent scan cells to produce the scan chain. Each of the scan cells also have a functional input latch that is coupled to an output of one combinational logic block and a functional output latch that is coupled to the input of another combinational logic block.
One type of combinational logic block is a domino circuit. During normal operation of a domino circuit, a clock is deasserted to precharge an output node to a high logic level while the output of a first latch (input to the domino circuit) and other inputs to the domino circuit transitions to and stabilizes at the desired logic levels. Then, the clock is asserted to conditionally discharge (evaluate) the output node depending on the inputs to the domino circuit. A second latch is coupled to receive the output of the domino circuit and configured to be transparent while the clock is asserted. When the clock is again deasserted, the second latch is closed such that the output of the domino circuit is stored within the second latch before the output node is again precharged.
The output node is discharged if the input signals to the domino circuit enable a discharge path from the output node to the ground node. The domino circuit is configured such that a discharge path is not enabled when the desired output is a high logic level for a particular combination of input values (permitting the output node to remain at its high logic level established during the precharge phase) and enabled when the desired output is a low logic level for a particular combination of input values.
The following method is used to test the operation of dynamic circuits, such as domino logic, by using scan testing. First, a sequence of bits are applied to the head of the scan chain until all the scan cells have been initialized to the desired values. The stimulus is then applied to the domino logic through a functional output latch and each response is captured by a corresponding functional input latch at an output of the domino circuit. The output of each domino circuit is serially shifted out through the scan output latches to the tail of the scan chain to be compared against expected values. Should a domino circuit not discharge an output node during the time provided or should the domino circuit be defective such that it discharges the output when it should not or does not discharge the output when it should, the response will not correspond to the expected value and the device will fail the test.
During the scan shift operation, the clock may be asserted (indicating an evaluation phase) or deasserted (indicating a precharge phase). Testing dynamic circuits, such as domino logic, under either condition presents problems.
If the clock is left in an asserted state (evaluate phase) during the scan shift operation, the toggling data may trigger a spurious discharge of the output node.
It is important that the inputs to the domino circuit are stable at the desired values when during an evaluation phase in order to avoid generating an incorrect output. If an input signal temporarily transitions through a logic level other than the desired logic level during the scan shift operation performed in the evaluation phase such that the combination of input values at any instant enables a discharge path through the domino circuit, the output may be discharged to the low logic level. The output remains discharged until the next precharge phase even if the input values attain their desired values and these desired values do not enable a discharge path. Thus, even if the desired input values correspond to an output at the high logic level, the spurious discharge causes the output to transition to and remain at the low logic level.
One method to avoid a spurious discharge if the clock is left in the asserted state is to include logic coupled to receive the output of the scan cell and a test mode signal to generate a new output which does not toggle during the scan shift operation. A scan cell which does not toggle during the scan shift operation is known as a non-destructive scan cell. During the scan shift operation, the test mode input is asserted, causing the logic to force the new output to a value which will not cause the combinational logic to discharge the output node. For example, the logic may simply be a nor gate coupled to receive the output signal and a test mode signal to generate a new output being the same as the output signal when the test mode signal is deasserted and a logic low level when the test mode signal is asserted. When the scan shift operation is completed, the test mode input is deasserted, causing the logic to force the new output to the desired value. Although the use of an extra control signal (the test mode signal) and this additional logic avoids the spurious discharge during the scan shift operation, it also requires a more complex scan cell which adds to the cost of the integrated circuit particularly since the scan cells are typically replicated in numerous latches and flip-flops throughout the integrated circuit.
If the clock is left in a deasserted state (precharge phase), the scan latch data stored in that internal node may be corrupted. The first scan latch (functional output latch of a first scan cell) that drives an input of a domino circuit is transparent when the clock is deasserted (precharge phase) and the second scan latch (functional input latch of a second scan cell) that latches the output of the domino circuit is transparent when the clock is asserted (evaluate phase). However, during the scan shift operation, the data is serially scanned through each of these scan cells via a scan input latch and scan output latch (scan latching) as opposed to the functional input latch and functional output latch (functionally latching). If the clock is left in a deasserted state, the functional input latch of the scan cell is enabled during the scan shift operation. Therefore, both the scan input latch and the functional input latch drive the same internal node. Thus, the scan latch data stored in that internal node may be corrupted.
One method to avoid corruption of data if the clock is left in the deasserted state is to add logic to enable control of the scan cell latch such that the scan cell latch is only transparent if the clock is deasserted and a test mode signal is deasserted. During a scan shift operation, the test mode signal is asserted thereby disabling the first scan cell latch despite the deassertion of the clock signal. When the scan shift operation is completed, the clock signal is asserted (evaluate phase) and then the test mode signal is deasserted thereby continuing to disable the first scan cell latch. The output is latched by the second scan cell latch when the clock signal is deasserted. Thus, the critical period begins at the time the clock signal is asserted and ends when the clock signal is deasserted. This method does require an extra control signal (the test mode signal). The additional control signal and logic adds complexity and cost to the integrated circuit.
What is needed is a method and apparatus to perform scan testing of dynamic circuits, such as domino logic, which do not require an additional control signal.